GitHub

fpga-projects

RTL Design and Verification of a 4-bit Synchronous Up/Down Counter using Verilog HDL, featuring parallel load, enable control, ripple carry output, simulation, synthesis, and FPGA implementation in ...
IEEE

FPGA Implementation of PoolFormer Network Using Python-Driven High-Level Synthesis Framework for Edge-AIoT Speech Recognition

Abstract: This brief presents an edge-AIoT speech recognition system, which is based on a new spiking feature extraction (SFE) method and a PoolFormer (PF) neural network optimized for implementation ...
GitHub

Pyrefly: A fast type checker and language server for Python with powerful IDE features

Pyrefly is a type checker and language server for Python, which provides lightning-fast type checking along with IDE features such as code navigation, semantic highlighting, and code completion. It is ...
IEEE

An Efficient FPGA-Based Edge AI System for Railway Fault Detection

Abstract: Binary neural networks (BNNs), characterized by 1 bit-width weights and activations, are well-suited for deployment on edge computing platforms such as field-programmable gate arrays (FPGAs) ...