IEEE

Design and Experimental Verification of a 6.25-GHz PLL for Harsh Temperature Conditions in 65-nm CMOS Technology

Abstract: Reliability is an important characteristic of electronic systems, and it could be undermined by several issues. Among these, a wide temperature range represents a threat to the correct ...
IEEE

A Dual-Path SPD/PFD PLL With PVT-Insensitive Loop Bandwidth

Abstract: This work presents an 8.5–14 GHz dual-path sampling phase detection (SPD)/phase frequency detection (PFD) phase-locked loop (PLL) (DP-SPFDPLL), with extended frequency/phase detection ranges ...