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GitHub8d

This is an attempt to fine tune SOTA Large Language Models so as to generate Verilog (VHDL) programmes, detect syntax, logic and human errors in codes and rectify them.

├── .gitignore ├── LICENSE ├── README.md ├── environment.yaml ├── requirements.txt ├── data │ └── df_small.csv │ └── formatted_small_df.csv ├── preprocessing │ └── data_preprocessing.py ...
GitHub9d

Automated Code Correction Framework

The Automated Code Correction Framework is an AI-powered debugging tool designed to automate error detection and correction. It streamlines the debugging process by ...