IEEE

Design Optimization of Flip FET Standard Cells With Dual-Sided Pins for Ultimate Scaling

Abstract: Recently, we proposed a novel transistor architecture for 3-D stacked FETs called Flip FET (FFET), featuring N/P transistors back-to-back stacked and dualsided interconnects. With dual-sided ...
IEEE

Modeling of Inter-Turn Short Circuits in a Multiphase Synchronous Motor Using Power-Sharing Capability

Abstract: This article explores the modeling of inter-turn short circuits (ITSCs) in segmented permanent magnet synchronous machines, with a focus on highly coupled segmentation (HCS) and multisector ...
IEEE

Design and Analysis of Master Slave D Flip Flop Using Pass Transistor

Abstract: This article presents a novel approach to implementing a positive-edge triggered D flip-flop utilizing pass transistors, aiming to offer improved performance and energy efficiency. The ...
IEEE

Design and Test of High-Low Voltage Excitation System for HTS Synchronous Condenser

Temperature superconducting (HTS) synchronous condenser is a reactive power compensation device with the advantages of low loss, high efficiency and wide reactive power range. Therefore, it has a very ...
IEEE

Virtual Synchronous Machine Design for Islanded Microgrids Using the Extended Impedance Criterion With Grid Frequency Dynamics Included

Abstract: Virtual synchronous machine (VSM) control is commonly used to control power converters in islanded microgrids (MGs). Frequently, the dynamic model of the MG is unknown and, therefore, the ...
IEEE

Secured Lightweight TRNG Design Using Encrypt Flip-Flop Architecture

Abstract: The development of a True Random Number Generator (TRNG) is crucial for enhancing security in a cryptographic system, or in general where high unpredictability is insisted upon. True ...
IEEE

Enhanced State and Unknown Input Estimation for Synchronous Reluctance Motor Using Takagi-Sugeno Fuzzy Proportional Multi-Integral Observer

Abstract: This study introduces a novel approach to enhance state and unknown input estimation for the synchronous reluctance motor, utilizing the Takagi-Sugeno fuzzy representation. A proportional ...
IEEE

Clock-Aware Register Migration for Multi-Bit Flip-Flop Generation in Low-Power Design

Abstract: The continuous technological advancements in modern SoC design have introduced significant power challenges, with over 30 % of power consumption attributed to the clock network. The ...
IEEE

Synchronous Boost Converter Design for an E-Scooter Application and Comparison with Conventional Boost Converter

Abstract: This study presents the performance of a designed Synchronous Boost Converter for an E-Scooter application and compares it with a Conventional Boost Converter. The study's primary objective ...
IEEE

Enhanced Design and Electromagnetic Analysis of Synchronous Reluctance Machines Using Multi-Material Additive Manufacturing

Abstract: This article comprehensively investigates the design and simulation of synchronous reluctance machines (SynRMs) using multi-material additive manufacturing (MMAM) methods. The main goal is ...