Hence, it relieves the system’s CPU from the task of polling in a multi-level priority system. This paper deals with implementation of a priority interrupt controller using Verilog language.

I wanted to write a post about doing state machines in Verilog and target the Lattice iCEstick board that we often use for quick FPGA projects.

Thanks to the [turbo9team], however, you can now host one of these CPUs — maybe even a better version — in an FPGA using Verilog.