About SiFive SiFive is the leading provider of processor cores, accelerators, and SoC IP to create domain-specific architecture based on the free and open RISC-V instruction set architecture.

Evaluation methodology/metrics and caveats, instruction set design, advanced pipelining, instruction level parallelism, prediction-based techniques, alternative architectures (VLIW, Vector and SIMD), ...

As part of the collaboration, Fractile will integrate Andes Technology’s high-performance RISC-V vector processor with its own groundbreaking in-memory computing architecture via ACE.

It will be the first to open-source its unified RISC-V Vector CPU-with-GPU Instruction Set Architecture (ISA) and provide register-level access to its hardware via a Hardware Abstraction Layer (HAL).

Our new open-standard patented C-GPU architecture combines a RISC-V Vector CPU core with Vulkan enabled GPU and AI/ML extensions to bring highly efficient graphics, compute, and AI/ML functionalities ...

Andes’ fifth generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, ...