EDN

Synopsys announces SystemVerilog testbench

At the SNUG (Synopsys Users Group) East meeting this week in Boston, Synopsys will release Pioneer-NTB, its new automatic testbench-verification system supporting the SystemVerilog design and ...
EDN

Synopsys ‘pioneers’ SystemVerilog testbench tool

SANTA CRUZ, Calif. — Synopsys Inc. is bringing the “ecosystem” built around its VCS Verilog simulator to users of third-party simulators with Pioneer-NTB, a SystemVerilog testbench automation tool ...
Electronic Design

Tool Automates Generation Of SystemVerilog Testbenches

The SystemVerilog infrastructure is built out further with Synopsys' introduction of Pioneer-NTB. This testbenchautomation tool delivers native SystemVerilog testbench generation to users of ...
Hackaday

FPGA Testbenches Made Easier

You finally finish writing the Verilog for that amazing new DSP function that will revolutionize human society and make you rich. Does it work? Your first instinct, of course, is to blow it into your ...
Business Wire

SpringSoft’s Verdi Debug Software Expands Verification Interoperability with Comprehensive UVM Support

HSINCHU, Taiwan--(BUSINESS WIRE)--SpringSoft, Inc., a global supplier of specialized IC design software, today announced comprehensive support for the Universal Verification Methodology (UVM) with its ...
Semiconductor Engineering

Optimizing Testbench Acceleration Performance

Part 3 in a series of papers that demystify the performance of SystemVerilog and UVM testbenches when using an emulator for the purpose of hardware-assisted testbench acceleration. In these three ...
Semiconductor Engineering

Testbench Acceleration Performance Demystified

Part 2 in a series of papers that demystify the performance of SystemVerilog and UVM testbenches when using an emulator for the purpose of hardware-assisted testbench acceleration. In these three ...