We were contacted by [morbo] to let us know about a project on the AdaCore blog that concerns programming a PicoRV32 RISC-V softcore with Ada. The softcore itself runs on a Lattice ICE40LP8K-based ...

Targeted, preconfigured RISC-V IP cores plus low-risk, easy-start, deferred-payment IP licensing make embedded RISC-V design easier than ever Santa Clara, California, RISC-V Summit — October 22, 2025 ...

CEVA-BX1 and CEVA-BX2 Audio DSPs and audio front-end software to be available through Intel Pathfinder for RISC-V ROCKVILLE, Md., Dec. 1, 2022 /PRNewswire/ -- CEVA, Inc. (NASDAQ: CEVA), the leading ...

This program is a new way for embedded system developers to adopt RISC-V processors faster and with less risk. Catalyst combines CAST’s 32-bit RISC-V processor IP cores with simplified configurations, ...

BANGKOK, Dec. 12, 2019 /PRNewswire/ -- RISC-V Summit -- The trend towards compute intensive gateways and edge devices is driving the integration of traditional deterministic control applications with ...

READING, United Kingdom, May 28, 2025 — Aion Silicon (formerly Sondrel), an ASIC and SoC architecture partner, today announced it has secured a $12 million engagement to provide design services for a ...

Another presentation is still being coordinated. More information can be found on the conference website.

SAN MATEO, Calif., Nov. 28, 2017 /PRNewswire/ -- SiFive announced today that it has joined GLOBALFOUNDRIES' FDXcelerator™ Partner Program, and will be making RISC-V CPU IP including SiFive's E31 and ...

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CAST, the semiconductor intellectual property provider, has unveiled the CAST Catalyst Program. This program is a new way for embedded system developers to adopt RISC-V processors faster and with less ...