Business Wire

MathWorks Speeds Up FPGA-in-the-Loop Verification

NATICK, Mass.--(BUSINESS WIRE)--MathWorks today announced new capabilities in HDL Verifier to speed up FPGA-in-the-loop (FIL) verification. The new FIL capabilities enable faster communication with ...
Design-Reuse

Microsemi Collaborates with MathWorks to Deliver First Integrated FPGA-in-the-Loop Workflow for PolarFire and SmartFusion2 FPGA Development Boards

ALISO VIEJO, Calif. -- April 19, 2018-- Microsemi Corporation (Nasdaq: MSCC), a leading provider of semiconductor solutions differentiated by power, security, reliability and performance, today ...
New Electronics

MathWorks enhances range with fpga and asic coding and verification products

In a move described as a 'significant enhancement' to its product range, MathWorks has launched HDL Coder, which allows HDL code to be generated directly from MATLAB and used to implement fpgas and ...
Electronics Weekly

MathWorks couples MATLAB with FPGA design flow

MathWorks has coupled its MATLAB design tool more closely to FPGA design. It has introduced a software tool which automatically generates HDL code from MATLAB for implementing FPGA and Asic designs ...
EDN

Product how-to: Achieving STARC and DO-254 compliance using HDL Coder-generated code

HDL Coder generates target independent, synthesizable Verilog and VHDL code from MATLAB functions, Simulink models, and Stateflow charts. The generated HDL code is bit-true and cycle-accurate to ...