EDN

Xilinx ISE 12 adds intelligent clock gating

SAN FRANCISCO—Xilinx Inc. Monday (May 3) introduced a new version of its ISE Design Suite to support its Virtex-6 and Spartan-6 FPGA families. According to the company, ISE 12 adds intelligent clock ...
Design-Reuse

Xilinx ISE Design Suite 12 Enables Up to 30% Dynamic Power Reduction with Intelligent Clock-Gating Technology

AMBA 4 AXI4 IP Support and Innovations in Design Preservation Combined with ISE Power Optimization to Deliver New Levels of Productivity for Virtex-6 and Spartan-6 FPGAs SAN JOSE, Calif., May 3, 2010- ...