Design-Reuse

IP core-centric communications protocol Introducing Open Core Protocol 2.0

Talking about IP core plug-and-play reuse, it is now generally admitted that cores need to be decoupled both from the on-chip interconnect and from one another using a clearly-specified core interface ...
Embedded

Defining standard Debug Interface Socket requirements for OCP-Compliant multicore SoCs: Part 1

Enabling a robust on-chip debug capability is being recognized as animportant Design for Debug (DFD) capability for complex SoC and having DFDstandardization makes the Open Core Protocol (OCP) ...
MusicRadar

Antelope Audio gets even more Zen with the USB version of the Q Synergy Core audio interface

Antelope Audio has unveiled a USB version of its Zen Q Synergy Core audio interface. This sits alongside the previously released Thunderbolt version. Functionally, this appears to be pretty much the ...
Design-Reuse

Enhance your High-Density data processing capabilities to new heights with the USB 3.2/ PCIe 3.1/ SATA 3.2 Combo PHY IP Core interface in 28HPC+/HPC process technology

4 th July 22. – T2M IP, the global independent semiconductor IP Cores provider & Technology experts, is pleased to announce the licensing of its partner’s USB 3.2/ PCIe 3.1/ SATA 3.2 Combo PHY IP Core ...